(1) Field of the Invention
This invention relates to the fabrication of integrated circuits and more particularly to a method for forming narrow trench isolation for integrated circuit devices.
(2) Description of the Prior Art
Recent advances in semiconductor processing technologies have dramatically increased the circuit density on a chip. Some chips formed from the semiconducting substrate contain more than a million devices and their minimum dimension are less than a micrometer in size.
One semiconducting technology area that must keep pace with this down sizing of the semiconductor device is the isolation technology. This isolation technology is used to electrically isolate the individual devices on the chip.
The electrical isolation used on some the first integrated circuits built consisted of an impurity diffused region around the individual device region having a dopant opposite in type to the device region. The electrical isolation was achieved by maintaining a reverse bias on the p-n junction. However, because the dopant diffused out from the isolation region during subsequent hot processing, down sizing was difficult to achieve and because of the high parasitic capacitance associated with the junction, circuit performance was poor. This technology was later replaced with an insulator having a high processing temperature and a reasonable low dielectric constant. The insulator of choice being silicon dioxide (SiO2) because it can be readily formed by oxidizing the silicon substrate.
This dielectric isolation, commonly referred to as LOCal Oxidation of Silicon (LOCOS), is still widely used in the semiconductor industry. The isolation is formed by masking the active device region with a oxidation barrier layer, such as silicon nitride (Si.sub.3 N.sub.4), and then oxidizing the exposed silicon in a oxidizing environment at high temperatures. For example, one can use steam at 900.degree. to 1200.degree. C. The area of the silicon substrate not covered by the silicon nitride layer is thermally oxidized forming a relatively thick silicon dioxide (SiO.sub.2) and consuming a portion of the silicon and forming a thick silicon dioxide, commonly referred to a the field oxide.
Although this LOCOS isolation is still widely used in the semiconductor industry, it is known to have a number of limitations which hinder the progress towards further down sizing, which is needed for ultra large scale integration (ULSI). For example, a recent paper titled "Sensitivity of Field Isolation Profiles to Active Pattern" by P. U. Kenkare et al in the technical digest of the international Electron Device Meeting in Washington D.C., December 1993 and published by the IEEE, cover some of these limitations as one scales down the isolation to submicrometer dimensions.
The principle limitation is the encroachment of the thermal oxide into the active device region under the Si.sub.3 N.sub.4 oxidation barrier mask. This lateral oxidation, usually referred to as the "birds beak" because of its shape, must be taken into consideration when lay out design of the circuit components and limits the packing density of the devices on the chip. Another limitation is the stress that results from the relatively thick field oxide. The thermal mismatch in the coefficient of expansion between the oxide and silicon lead to crystalline defects. For example, various types of crystal dislocation can occur, which degrade the electrical characteristics of the device. Still another limitation results from the increase in volume of the silicon dioxide compared to the volume of the silicon consumed in the reaction. This results in a non-planar surface with approximately one half of the SiO.sub.2 thickness lying above the plain of the substrate. This can adversely affect the photolithography because of the shallow depth of focus required for submicrometer images. To over come the topography problem the silicon substrate can be recessed in the field oxide areas prior to thermal oxidation so as to form a more planar surface and a silicon nitride deposited on the sidewall to eliminate the oxide encroachment into the device region. For example, see the paper entitled "High Speed Bipolar ECL Devices Using a Vertical Isolated Self-Aligned Transistor" by T. Fujita et al, Japanese Journal of Applied Physics, Vol. 22 (1983) Supplement 22-1, pp 125-128.
More recently a method for forming shallow trench isolation has been described by F. T. Liou et al, U.S. Pat. No. 5,130,268, in which a shallow trench having silicon oxide sidewalls is selectively and partially filled with epitaxial silicon and then completely oxidized to form an isolation which is planar with the substrate surface. However, an implant is required in the bottom of the trench before oxidation to prevent inversion from occurring that can cause high leakage currents between active device regions. Also, the oxide encroachment into the device still remains as a problem.
Another isolation technique is described by M. S. Liu, whereby a deep trench is formed and filled with a doped polysilicon for isolating bipolar devices. However, these deep trenches are more difficult to make at sub-micrometer widths and also more expensive.
Therefore, it would be very useful to have a low cost process for make shallow trenches which are submicrometer in width and avoid encroachment of the oxide into the device region. It would be an additional benefit to eliminate channel stopper implant that can cause crystal damage.